While I’m writing a DMAC on my Virtex-5 PCIe card, I’ve found that the “MAX_PAYLOAD_SIZE” register has only 3 bits, while the size will be between 128 and 4096. And here’s the answer:
3’b000 128B
3’b001 256B
3’b010 512B
3’b011 1024B
3’b100 2048B
3’b101 4096B
3’b110 Reserved
3’b111 Reserved
(from Xilinx application note XAPP1052 documentation).
and now I can continue!