Xilinx \u306e FPGA \u3092\u4f7f\u3044\u59cb\u3081\u305f\u306e\u306f 2001 \u5e74\u3060\u304b 2002 \u5e74\u3060\u304b\u3089\u3001\u3082\u304610\u5e74\u304f\u3089\u3044\u524d\u306b\u306a\u308b\u3002ISE \u304c 3.x \u3068\u304b 4.x \u3060\u3063\u305f\u6642\u4ee3\u3060\u3051\u3069\u3001\u57fa\u672c\u7684\u306b Project Navigator \u306e\u4f7f\u3044\u52dd\u624b\u306f\u5927\u304d\u304f\u5909\u308f\u3089\u306a\u304b\u3063\u305f (XST \u306e\u5408\u6210\u3068\u304b\u306f\u3001\u304b\u306a\u308a\u8ce2\u304f\u306a\u3063\u305f\u3051\u3069)\u3002
\nPlanAhead \u3063\u3066 FloorPlanner \u306e\u5f8c\u7d99\u3067\u3057\u3087\uff1f\u304f\u3089\u3044\u306b\u601d\u3063\u3066\u3044\u305f\u306e\u3060\u304c\u3001\u3069\u3046\u3084\u3089\u9055\u3046\u3057\u3001\u3057\u304b\u3082 Project Navigator \u306b\u4ee3\u308f\u3063\u3066 ISE \u306e\u9854\u306b\u306a\u308b\u3089\u3057\u3044\u3001\u3068\u3044\u3046\u3053\u3068\u3067\u3001\u5148\u65e5\u5927\u962a\u3067\u8b1b\u7fd2\u4f1a\u53d7\u3051\u3066\u304d\u305f\u3002\u3053\u308c\u306f\u3059\u3054\u3044\u30c4\u30fc\u30eb\u3060\u305e\u3001\u3068\u3044\u3046\u5370\u8c61\u3002\u305d\u308c\u3067\u3001\u4eca\u56de\u306f\u6771\u4eac\u3067 ISE 13.1 \u3068\u304b\u306e\u304a\u8a71\u3002
\n[\u524d\u7f6e\u304d]
\nVirtex-7, Zynq-7000: \u5927\u304d\u3059\u304e\u3066\u3072\u3068\u308a\u3067\u8a2d\u8a08\u3059\u308b\u306e\u306f\u5927\u5909\u306a\u306e\u3067\u3001\u30c1\u30fc\u30e0\u8a2d\u8a08\u4f53\u5236\u3084 IP \u306e\u6d3b\u7528\u304c\u91cd\u8981\u3002
\n– ISE 13.1 \/ PlanAhead = \u30c1\u30fc\u30e0\u3067\u8a2d\u8a08\u3059\u308b\u305f\u3081\u306e\u30ad\u30fc
\n– AXI4
\n\u3068\u3044\u3063\u305f\u3042\u305f\u308a\u304cXilinx\u306e\u63d0\u6848\u3059\u308b\u89e3\u6c7a\u7b56\u3002
\n[PlanAhead 13.1 \u7de8\u306e\u30e1\u30e2]
\n– PlanAhead 13.1 \u3067\u306f ISIm \u3082\u30b5\u30dd\u30fc\u30c8\u3057\u3066\u3044\u308b\u3002\u65b0\u3057\u3044 ISim \u304c\u3069\u308c\u304f\u3089\u3044\u30a4\u30b1\u3066\u308b\u304b\u306f\u308f\u304b\u3089\u3093\u304c\u30fb\u30fb\u30fb (\u500b\u4eba\u7684\u306b\u306f\u30bd\u30fc\u30b9\u304c\u5909\u308f\u308b\u3068\u6bce\u56de\u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u3092\u7d42\u4e86\u3057\u306a\u3044\u3068\u3044\u3051\u306a\u3044(\u3088\u3046\u306a\u6c17\u304c\u3059\u308b\u3093\u3060\u3051\u3069\u89e3\u6c7a\u6cd5\u304c\u3042\u308b\u306e\u304b\u3082\u3057\u308c\u306a\u3044)\u70b9\u304c\u975e\u5e38\u306b\u4e0d\u670d)
\n– RTL \u30bd\u30fc\u30b9\u30d5\u30a1\u30a4\u30eb\u3092\u5165\u308c\u305f\u3068\u304d\u306b\u3001simulation testbed \u3082\u4e00\u7dd2\u306b\u5165\u3063\u3066\u3057\u307e\u3046\u306e\u3067\u3001\u305d\u308c\u306f simulation testbed \u306e\u307b\u3046\u306b\u624b\u52d5\u3067\u79fb\u52d5\u3059\u308b\u5fc5\u8981\u304c\u3042\u308b\u3002
\n– \u30b9\u30c8\u30e9\u30c6\u30b8\u3092\u9078\u3093\u3060\u3068\u304d\u306b\u3001\u5404\u30c4\u30fc\u30eb\u306e\u30aa\u30d7\u30b7\u30e7\u30f3\u3067\u30c7\u30d5\u30a9\u30eb\u30c8\u5024\u3067\u306a\u3044\u3082\u306e\u306b\u306f * \u304c\u4ed8\u304f\u3002
\n– \u6700\u8fd1\u306f Coregen \u3067\u30e1\u30e2\u30ea\u30d6\u30ed\u30c3\u30af\u3092\u4f5c\u308b\u3068\u304d\u306b\u3001BlockRAM \u306e\u6d88\u8cbb\u96fb\u529b\u3092\u898b\u7a4d\u3082\u308c\u308b\u3089\u3057\u3044\u3002
\n– PlanAhead \u3067\u306f\u3069\u3053\u304b\u306e\u30a6\u30a3\u30f3\u30c9\u30a6\u3067\u4f55\u304b\u3092\u9078\u629e\u3059\u308b\u3068\u3001\u307b\u304b\u306e\u30a6\u30a3\u30f3\u30c9\u30a6\u306b\u5bfe\u5fdc\u3059\u308b\u3082\u306e\u304c\u3042\u3063\u305f\u5834\u5408\u306b\u305d\u308c\u3082\u9078\u629e\u3055\u308c\u308b\u3002\u3053\u308c\u3001\u805e\u3044\u305f\u3060\u3051\u3060\u3068\u306a\u3093\u3060\u304b\u3088\u304f\u308f\u304b\u3093\u306a\u3044\u3093\u3060\u3051\u3069\u3001\u5b9f\u969b\u306b\u89e6\u3063\u3066\u307f\u308b\u3068\u3061\u3087\u3063\u3068\u3059\u3054\u3044\u30a4\u30f3\u30bf\u30d5\u30a7\u30a4\u30b9\u3060\u3068\u601d\u3046\u3002\u30af\u30ed\u30b9\u9078\u629e\u3068\u3044\u3046\u305d\u3046\u3060\u3002
\n– \u306a\u3093\u3068\u306a\u304f\u6c17\u3065\u3044\u3066\u305f\u3093\u3060\u3051\u3069\u3001\u6700\u8fd1\u306f Map \u3067 technology mapping \u3068\u540c\u6642\u306b timing driven synthesis \u3082\u3059\u308b\u306e\u306d\u3002\u3044\u3064\u306e\u307e\u306b\u304b Map \u306b\u305a\u3044\u3076\u3093\u6642\u9593\u304b\u304b\u308b\u3088\u3046\u306b\u306a\u3063\u305f\u306a\u3042\u3001\u3068\u601d\u3063\u3066\u305f\u3093\u305f\u304c\u3001\u305d\u308a\u3083\u6642\u9593\u304b\u304b\u308b\u308f\u306a\u3002
\n– Schematic view \u3067 timing path \u3092\u307f\u308b\u3068\u304d\u306b\u3001\u5358\u4e00\u306e\u30d1\u30b9\u3060\u3051\u3058\u3083\u306a\u304f\u3066\u8907\u6570\u306e\u30d1\u30b9\u3092\u9078\u629e\u3057\u3066\u4e00\u6c17\u306b\u56de\u8def\u56f3\u3092\u63cf\u304f\u3053\u3068\u3082\u3067\u304d\u308b\u3002\u9045\u3044\u65b9\u306e\u30d1\u30b9\u3092\u307e\u3068\u3081\u3066\u307f\u3089\u308c\u308b\u306e\u306f\u4fbf\u5229\u305d\u3046\u3002
\n– netlist_hierarchy=rebuilt \u91cd\u8981\u3002XST default.
\n– \u81ea\u52d5\u751f\u6210\u3057\u305f PBlock \u3092\u305d\u306e\u307e\u307e\u4f7f\u3046\u306e\u306f\u3042\u307e\u308a\u3088\u304f\u306a\u3044\u3002\u3061\u3083\u3093\u3068\u81ea\u5206\u3067\u8003\u3048\u3066\u4fee\u6b63\u3059\u308b\u3079\u304d\u3068\u306e\u3053\u3068\u3002
\n– PlanAhead 13.1 \u3067\u306f resource usage \u304c\u30cd\u30c3\u30c8\u30ea\u30b9\u30c8\u968e\u5c64\u3054\u3068\u306b breakdown \u3055\u308c\u3066\u898b\u3089\u308c\u308b\u307d\u3044\u3002\u3053\u308c\u306f\u3044\u3044\u3002
\n– \u3088\u308a\u3088\u3044\u30c7\u30b6\u30a4\u30f3\u306e\u305f\u3081\u306b\u3001DRC \u306e\u8b66\u544a\u306f\u3061\u3083\u3093\u3068\u8aad\u307f\u307e\u3057\u3087\u3046\u3002
\n– Slack histogram \u4fbf\u5229\u3060\u306a\u3002log scale \u304a\u3059\u3059\u3081\u3002slack \u304c\u8db3\u308a\u306a\u3044 bin \u306e\u30d1\u30b9\u3092\u5168\u90e8\u51fa\u3057\u3066\u3001\u305d\u308c\u304c\u3069\u3053\u901a\u3063\u3066\u308b\u304b\u78ba\u8a8d\u3057\u3066\u30fb\u30fb\u30fb
\n– \u30e2\u30b8\u30e5\u30fc\u30eb\u3092\u3044\u304f\u3064\u304b\u9078\u3093\u3067 cycle color. \u30ec\u30a4\u30a2\u30a6\u30c8\u3092\u78ba\u8a8d\u3059\u308b\u3068\u304d\u306b\u3053\u308c\u4fbf\u5229\u3002
\n– \u8907\u6570\u306e run set \u3092\u4f7f\u3063\u305f\u5834\u5408\u306f Design runs \u3092\u307f\u308b\u3068\u3001\u7d50\u679c\u306e\u307e\u3068\u3081\u4e00\u89a7\u304c\u6bd4\u8f03\u3067\u304d\u308b (\u3059\u3052\u3048)\u3002
\n– \u8907\u6570\u306e\u5236\u7d04\u30bb\u30c3\u30c8\u3092\u4f5c\u308b\u5834\u5408\u306b\u306f\u3001\u65b0\u3057\u3044\u5236\u7d04\u304c\u66f8\u304d\u8fbc\u307e\u308c\u308b\u30d5\u30a1\u30a4\u30eb (target UCF) \u3092\u6307\u5b9a\u3057\u3066\u304a\u304f\u3002\u3053\u308c\u306b\u3088\u3063\u3066\u8907\u6570\u306e floorplan \u3068\u304b\u3092\u8a66\u3059\u3053\u3068\u304c\u3067\u304d\u308b\u3002
\n– PlanAhead \u306f\u8907\u6570\u306e run set \u3092\u3054\u308a\u3054\u308a\u3084\u308b\u5834\u5408\u306e\u30b8\u30e7\u30d6\u7ba1\u7406\u3092\u52b9\u7387\u3088\u304f\u3084\u308c\u308b\u3002\u3053\u308c\u306f Makefile (remote spawning \u304c\u3067\u304d\u306a\u3044) \u3068\u304b LSF \u3092\u4f7f\u3046\u3088\u308a\u3044\u3044\u3001\u3068\u306e\u3053\u3068\u3002\u307e\u3042\u3001\u305d\u3046\u3060\u306a\u3002
\n– UG702 (\u90e8\u5206\u518d\u69cb\u6210) \u3068\u304b UG748 (\u968e\u5c64\u30c7\u30b6\u30a4\u30f3\u624b\u6cd5) \u306f\u3061\u3083\u3093\u3068\u8aad\u307f\u305f\u3044\u3002
\n– Project Navigator \u3092 discontinue \u3059\u308b\u4e88\u5b9a\u306f\u4eca\u306e\u3068\u3053\u308d\u306a\u3044\u3068\u306e\u3053\u3068\u3002
\n– EDK \u3068\u306e\u7d71\u5408\u306f\u3053\u308c\u304b\u3089\u3002
\n– PlanAhead \u306f\u57fa\u672c\u7684\u306b\u30aa\u30f3\u30e1\u30e2\u30ea\u3067\u3084\u308a\u305f\u3044\u3093\u3060\u3051\u3069\u3001XST \u304b\u3089\u5148\u306e\u30c4\u30fc\u30eb\u306f Project Navigator \u3068\u3044\u307e\u306e\u3068\u3053\u308d\u5171\u901a\u3002\u65b0\u3057\u3044\u5408\u6210\u30c4\u30fc\u30eb\u306f\u5b8c\u5168\u306b PlanAhead \u306b integrate \u3055\u308c\u3066\u7269\u7406\u5408\u6210\u3092\u3084\u308b\u3088\u3046\u306b\u306a\u308b\u3001\u4e88\u5b9a (14.x \u4ee5\u964d\u306e\u3069\u3053\u304b\u3067)\u3002
\n[AMBA AXI4 \u7de8\u306e\u30e1\u30e2]
\nAXI4 \u306f\u65e2\u5b58\u306e on-chip bus \u306b\u4ee3\u308f\u308b\u3082\u306e\u3002
\n– AXI4 (\u3075\u3064\u3046\u306ebus)\u3001AXI4-Lite (\u30ec\u30b8\u30b9\u30bf\u30d9\u30fc\u30b9\u3067\u30d0\u30fc\u30b9\u30c8\u304c\u3067\u304d\u306a\u3044)\u3001AXI4-Stream (\u30a2\u30c9\u30ec\u30b9\u304c\u306a\u3044\u30c7\u30fc\u30bf\u30b9\u30c8\u30ea\u30fc\u30e0) \u306e3\u3064\u3002
\n– Master \u3068 slave \u306e\u30af\u30ed\u30c3\u30af\u304c\u540c\u4e00\u3067\u306a\u304f\u3066\u3082\u3088\u3044\u3002
\n– Master \u3068 slave \u306e\u4fe1\u53f7\u306e\u52d5\u304d\u306f\u3060\u3044\u305f\u3044\u5bfe\u79f0\u3002
\n– \u73fe\u5728\u306f\u8907\u6570\u306e\u30e2\u30b8\u30e5\u30fc\u30eb\u3067\u5916\u90e8\u30e1\u30e2\u30ea\u3092\u5171\u6709\u3059\u308b\u305f\u3081\u306e MPMC (multi-port memory controller) \u307f\u305f\u3044\u306a\u306e\u304c\u3042\u308b\u308f\u3051\u3060\u3051\u3069\u3001AXI4 \u3067\u30a4\u30f3\u30bf\u30d5\u30a7\u30a4\u30b9\u304c\u7d71\u4e00\u3055\u308c\u308b\u306e\u3067\u4fbf\u5229\u3067\u3059\u3088\u30fc (\u3067\u3082\u305d\u308c\u3063\u3066\u30a2\u30af\u30bb\u30b9\u7cfb\u306e\u30bf\u30a4\u30df\u30f3\u30b0\u3092\u304e\u308a\u304e\u308a\u307e\u3067\u716e\u8a70\u3081\u3066\u3001\u307f\u305f\u3044\u306a\u8a2d\u8a08\u3067\u304d\u3093\u306e\u304b\u306a\u3002\u96e3\u3057\u305d\u3046\u3002\u3067\u3082\u5916\u90e8\u30e1\u30e2\u30ea\u30b3\u30f3\u30c8\u30ed\u30fc\u30e9\u306e\u4f7f\u3044\u65b9\u3068\u304b\u7d76\u5bfe\u697d\u306b\u306a\u308b\u3088\u306d)\u3002
\n– \u57fa\u672c\u7684\u306b\u306f ACLK, TDATA, TVALID, TREADY \u306e4\u3064\u306e\u4fe1\u53f7\u3067\u52d5\u304f\u3002\u7c21\u5358\u3002\u30a2\u30c9\u30ec\u30b9\u3068\u30c7\u30fc\u30bf\u3068\u304b\u306f multiplex \u3057\u306a\u3044\u3067\u5225\u3005\u306e\u30c1\u30e3\u30cd\u30eb\u3092\u4f7f\u3046\u3002\u57fa\u672c\u7684\u306b5\u30c1\u30e3\u30cd\u30eb\u5fc5\u8981 (address read\/write + data read\/write + write response) \u3002
\n– Lite \u3067\u306f\u30d0\u30fc\u30b9\u30c8\u304c\u306a\u3044\u306e\u3067\u3001\u30a4\u30f3\u30bf\u30d5\u30a7\u30a4\u30b9\u306f\u304b\u306a\u308a\u7c21\u7565\u5316\u3055\u308c\u308b\u3002
\n– Xilinx \u306e AXI4-Lite IP \u306f 32bit \u5e45\u306e\u307f
\n– AXI4-Stream + DMAC \u3068\u304b\u3067\u3046\u306b\u3087\u3046\u306b\u3087\u3057\u305f\u3044\u3002\u305d\u306e\u3078\u3093\u3069\u3046\u306a\u3093\u3060\u3002
\n– AXI4 interconnect \u306e IP core \u306f EDK \u306e\u30e9\u30a4\u30bb\u30f3\u30b9\u304c\u5fc5\u8981\u3002CPU (\u30d0\u30b9\u30de\u30b9\u30bf) \u306a\u3057\u3067\u3044\u3051\u308b\u304b\u3069\u3046\u304b\u3082\u554f\u984c\u3063\u307d\u3044 (\u3053\u308c\u306f\u305f\u3076\u3093\u554f\u984c\u306a\u3044\u3093\u3060… \u304c\u3001\u30e9\u30a4\u30bb\u30f3\u30b9\u306e\u554f\u984c\u306f\u53b3\u3057\u3044\u306a)\u3002
\n– PLB \u306e\u30b5\u30dd\u30fc\u30c8\u306f 14.1 \u307e\u3067\u3067\u7d42\u4e86\u3002PPC \u4f7f\u3063\u3066\u308b\u3072\u3068\u306f\u53b3\u3057\u3044\u306a\u30fb\u30fb\u30fb
\n– AXI \u306e\u30b5\u30dd\u30fc\u30c8\u306f\u57fa\u672c\u7684\u306b V6 \u4ee5\u964d\u3002
\n– V6 \u306f PLB \u3082 AXI4 \u3082\u4f7f\u3048\u308b (V6 \u306f PPC \u306a\u3044\u3051\u3069\u306d)
\n– PCIe – AXP4-Stream bridge \u304c\u4f7f\u3048\u308b\u3002\u3044\u307e\u306e\u30ed\u30fc\u30ab\u30eb\u30ea\u30f3\u30af\u3068\u306f\u9055\u3046\u30a4\u30f3\u30bf\u30d5\u30a7\u30a4\u30b9\u3002
\n– Platform studio \u3092\u4f7f\u308f\u305a\u306b AXI interconnect \u305d\u306e\u4ed6\u3092\u4f7f\u3046\u306b\u306f Xilinx Answer #37856 \u3092\u53c2\u7167\u3002
\n– Xilinx AXI Interconnect \u306b\u306f crossbar mode (\u901f\u3044\u304c\u5927\u304d\u3044) \u3068 shared access mode (\u5c0f\u3055\u3044) \u304c\u3042\u308b\u3002
\n– Master \u3068 slave \u304c\u76f4\u7d50\u3067\u304d\u308b\u3088\u3046\u306a\u5834\u5408\u306b\u306f pass-through mode\u3001\u3042\u308b\u3044\u306f 1to1 conversion mode.
\n– N to 1, 1 to N \u3082\u3042\u308b\u3002\u5fc5\u8981\u306a\u6a5f\u80fd\u3092\u9078\u3093\u3067\u4f7f\u3048\u3070\u3044\u3044\u3002
\n– Shared access mode \u3067\u306f read \/ write \u306e\u30a2\u30c9\u30ec\u30b9\u30fb\u30c7\u30fc\u30bf\u30c1\u30e3\u30cd\u30eb\u306b\u3064\u3044\u3066\u305d\u308c\u305e\u308c\u8abf\u505c\u304c\u884c\u308f\u308c\u3001\u540c\u6642\u306b\u8907\u6570\u306e\u30c8\u30e9\u30f3\u30b6\u30af\u30b7\u30e7\u30f3\u304c\u8d70\u3089\u306a\u3044\u3088\u3046\u306b\u306a\u308b\u3002
\n– \u4eca\u5f8c AXI Optimization Wizard \u307f\u305f\u3044\u306a\u306e\u304c\u3067\u304d\u308b\u4e88\u5b9a\u3002Size, frequency, latency, etc.<\/p>\n","protected":false},"excerpt":{"rendered":"
Xilinx \u306e FPGA \u3092\u4f7f\u3044\u59cb\u3081\u305f\u306e\u306f 2001 \u5e74\u3060\u304b 2002 \u5e74\u3060\u304b\u3089\u3001\u3082\u304610\u5e74\u304f\u3089\u3044\u524d\u306b\u306a\u308b\u3002ISE \u304c 3.x \u3068\u304b 4.x \u3060\u3063\u305f\u6642\u4ee3\u3060\u3051\u3069\u3001\u57fa\u672c\u7684\u306b Project Navigator \u306e\u4f7f\u3044\u52dd\u624b\u306f … “Xilinx \u6b21\u4e16\u4ee3FPGA\u8a2d\u8a08\u624b\u6cd5\u30bb\u30df\u30ca\u30fc: Mar.09, 2011” \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":""},"categories":[11,4],"tags":[],"class_list":["post-2618","post","type-post","status-publish","format-standard","hentry","category-11","category-4"],"_links":{"self":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2618","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/comments?post=2618"}],"version-history":[{"count":0,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2618\/revisions"}],"wp:attachment":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/media?parent=2618"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/categories?post=2618"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/tags?post=2618"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}