[ Keynote 3: Bringing FPGA Design to Application Domain Experts ]
\nDr. James Truchard @ National Instruments
\nNI LabVIEW: Enable graphical system design & verification in engineering, what spreadsheet does in finance.
\nMindstorm NXT \u304b\u3089 CERN \u306e\u52a0\u901f\u5668\u307e\u3067\u8a2d\u8a08\u3067\u304d\u308b\u305c\u3002
\nLong tail for real time application: low volume \u306a real time app \u3068\u3044\u3046\u306e\u306f\u305f\u304f\u3055\u3093\u3042\u308b\u3002High volume \u306a\u3082\u306e\u306f\u304c\u3093\u3070\u3063\u3066\u4f5c\u308c\u3070\u3044\u3044\u3051\u3069\u3001low volume \u306a\u3082\u306e\u306f LabVIEW \u3067\u4f5c\u308a\u307e\u3057\u3087\u3046\u3002
\nCompact RIO, a LabVIEW FPGA module.
\nRe-use drives IP abstraction levels.
\nUpgrade to new FPGA, board, chassis.
\nIP Plug’n’Play is required to accelerate innovation.
\n[Technology Issues Facing the World’s Largest Integrated Circuits]
\nStratix V \u306f12.5Gbps \u3068\u304b 28Gbps \u3068\u304b\u3067\u308b\u305c\u3001\u3068\u3044\u3046\u307b\u304b\u306f\u7279\u306b\u76ee\u65b0\u3057\u3044\u8a71\u306f\u306a\u3044\u304b\u306a\u3002100G Ether MAC \u304c\u8f09\u308b\u3089\u3057\u3044\u30fb\u30fb\u30fb
\nTSMC 28nm process, Power budget 2-20W for high-end FPGAs.
\n\u304a\u3063\u3068\u3001programmable power voltage \u3060\u3068\uff1f
\nQuartus \u304c\u81ea\u52d5\u7684\u306b\u96fb\u5727\u3092\u8a2d\u5b9a\u3059\u308b\u3089\u3057\u3044\u3002\u307e\u3058\uff1f
\nPartial reconfiguration, based existing incremental design & floorplanning tools. Can be controlled by soft logic or an external device.
\n\u7701\u96fb\u529b\u5316\u306b\u306f High-K metal gate \u304c\u52b9\u3044\u3066\u3044\u308b\u306e\uff1f
\n[Floating-point exponential functions for DSP-enabled FPGAs]
\nFloPoCo \u306e\u3072\u3068\u3002
\n\u5358\u7cbe\u5ea6\u3067\u306f\u3046\u307e\u304f\u30c6\u30fc\u30d6\u30eb\u5f15\u304d\u3092\u3084\u308b\u30c8\u30ea\u30c3\u30af\u3092\u3064\u304b\u3063\u3066\u304a\u308a\u3001BlockRAM\u3072\u3068\u3064\u3002\u500d\u7cbe\u5ea6\u3067\u3082\u30a2\u30c9\u30ec\u30b99bit x \u30c7\u30fc\u30bf95bit \u306a\u306e\u3067\u300136×512\u304c3\u3064\u3067\u3059\u306d\u3002
\nThe main messages of this talk:
\n– FPGA computing should be done the FPGA way and not by mimicking what processors do.
\n– Do I really need to compute this bit?
\n\u308f\u306f\u3002
\nFloPoCo \u3044\u3044\u3088\u306d\u3002
\n[Modular Design of Fully Pipelined Accumulators]
\n\u3075\u3064\u3046\u306e accumulator \u3068\u3044\u3046\u3088\u308a\u306f\u3001\u5165\u529b\u3092\u4e26\u5217\u306b\u3057\u3066\u304c\u30fc\u3063\u3068reduction\u6f14\u7b97\u3059\u308b\u611f\u3058\u306e\u3084\u3064\u3002\u524d\u4f5c\u306f\u52a0\u7b97\u5668\u30ab\u30b9\u30b1\u30fc\u30c9\u306b\u306a\u3063\u3066\u308b\u3002\u3053\u308c\u304c\u3061\u3083\u3093\u3068\u30d1\u30a4\u30d7\u30e9\u30a4\u30f3\u3067\u52d5\u304f\u306e\u306f\u30d1\u30ba\u30eb\u3060\u306a\u3002
\n\u3044\u3084\u3001\u306a\u3093\u304b\u3061\u3087\u3063\u3068\u7406\u89e3\u3067\u304d\u3066\u3044\u306a\u3044\u6c17\u304c\u3059\u308b\u3002
\n[Efficient implementation of Parallel BCD Multiplication in LUT-6 FPGAs]
\nBCD2bin + binary mult + bin2BCD \u3067\u306f\u306a\u304f\u3001\u305d\u306e\u307e\u307e\u3002
\n1. 0-9 \u306e\u6570\u5b57\u3092 Y^U (0, 5 or 10) \u3068 Y^L (-2 -1, 0, 1 or 2) \u306b recode \u3057\u3066\u51e6\u7406\u3002
\n2. \u90e8\u5206\u7a4d\u3092\u8a08\u7b97
\n3. BCD carry-ripple adder \u3067\u8db3\u3057\u3042\u308f\u305b\u308b
\n\u3053\u308c\u3061\u3087\u3063\u3068\u304a\u3082\u3057\u308d\u3044\u306a\u30021 \u3068 2 \u306f\u305d\u308c\u305e\u308c1\u30b9\u30c6\u30fc\u30b8\u3002
\n\u3086\u304f\u3086\u304f\u306f FloPoCo \u306b\u5165\u308c\u305f\u3044\u3089\u3057\u3044\u3002
\n[Lightweight DPA Resistant Solution on FPGA to Counteract Power Models]
\nDifferential Power Analysis \u304b\u3002AES \u306e\u4f8b\u3092\u3060\u3057\u3066\u305f\u3002
\n– Random inversion against hamming weight model
\n— All intermediate results are randomly inverted
\n— requires 1 bit RNG
\n– Random register renaming against hamming distance model
\n[An FPGA-Based Text Search Engine for Approximate Regular Expression Matching]
\nApproximate regex match \u304b\u3002
\nstring match \u3067\u306f smith-waterman systolic cell \u3068\u304b\u304c\u3042\u308b\u3051\u3069\u3001regex \u306e\u5b9f\u88c5\u4f8b\u306f\u306a\u3044\u3089\u3057\u3044\u3002
\napproximate \u3067\u8a08\u7b97\u3059\u308b\u305f\u3081\u306b edit distance \u3092\u4f7f\u3046\u3002
\nDP \u306e\u30c6\u30fc\u30d6\u30eb\u306e\u6a2a\u5e45\u306e\u5206\u3060\u3051\u30e2\u30b8\u30e5\u30fc\u30eb\u3092\u4e26\u3079\u308b\u3063\u307d\u3044\u306e\u3060\u304c\u5927\u4e08\u592b\u304b\u30fb\u30fb\u30fb
\n# of cells limits the pattern length. Max pattern length is 250 on current FPGA.
\n[Real-time Detection of Line Segments on FPGA]
\n\u90e8\u5c4b\u306e\u5199\u771f\u304b\u3089\u90e8\u5c4b\u306e\u5168\u90e8\u306e corner \u3092\u691c\u51fa\u3057\u305f\u308a\u3001\u9053\u8def\u306e\u30bb\u30f3\u30bf\u30fc\u30e9\u30a4\u30f3\u3068\u304b\u305d\u3046\u3044\u3046\u8981\u7d20\u3092\u305a\u3070\u30fc\u3063\u3068\u691c\u51fa\u3057\u305f\u308a\u3002\u3059\u3052\u30fc\u3088\u3059\u3052\u30fc\u3088\u3002\u4e38\u5c71\u7814\u3002
\n\u57fa\u672c\u7684\u306a\u3084\u308a\u65b9\u3068\u3057\u3066\u306f\u3001ELS (elementary line segment) \u3092\u898b\u3064\u3051\u3066\u3001\u305d\u308c\u3092\u305a\u305a\u305a\u3063\u3068 merge \u3057\u3066\u3044\u304f\u3002
\n\u54c1\u8cea\u306f\u3069\u3046\u3084\u3063\u3066\u691c\u8a3c\u3057\u3066\u3001\u3069\u3046\u3084\u3063\u3066\u300c\u691c\u51fa\u7d42\u4e86\u300d\u3068\u5224\u65ad\u3059\u308b\u306e\u304b\uff1f
\n[True Random Number Generation in Block Memories of Reconfigurable Devices]
\nGeneric TRNG module: 512×36 BRAM \u3067\u3001write collision \u3092\u8d77\u3053\u3059\u3002
\n\u3042\u30fc\u3053\u308c\u306f\u304b\u306a\u308a\u304a\u3082\u3057\u308d\u3044\u305e\u3002post processing \u306e\u65b9\u6cd5\u306b\u3082\u3088\u308b\u3093\u3060\u3051\u3069\u30017Mbps\u301c105Mbps\u306e\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u304c\u51fa\u308b\uff01
\nRing oscillator \u306a\u3093\u304b\u306b\u6bd4\u3079\u308b\u3068\u304b\u306a\u308a\u3044\u3044\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u3002
\nRobustness \u3082\u691c\u8a3c\u3057\u3066\u3044\u308b\u3002\u30e9\u30f3\u30c0\u30e0\u6027\u306e\u30c6\u30b9\u30c8\u306f\u30a8\u30f3\u30c8\u30ed\u30d4\u30fc\u306e\u5206\u5e03\u3067\u3084\u308c\u3070\u3044\u3044\u306e\u304b\u3002
\nPlacement \u304c\u5927\u4e8b\u304b\u3082\u3002\u5927\u4e8b\uff1f\u3093\u30fc\u3002\u5927\u4e8b\u3060\u3088\u306a\u3042\u3002\u304b\u306a\u308a\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"