{"id":2580,"date":"2010-06-01T18:06:10","date_gmt":"2010-06-01T09:06:10","guid":{"rendered":"http:\/\/yasu2.prosou.nu\/blog\/index.php\/2010\/06\/01\/heart_2010\/"},"modified":"2010-06-01T18:06:10","modified_gmt":"2010-06-01T09:06:10","slug":"heart_2010","status":"publish","type":"post","link":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2010\/06\/01\/2580\/","title":{"rendered":"HEART 2010"},"content":{"rendered":"

accept ratio was 54%.
\n[[ Session 1: FPGA-based Applications ]]
\n[ Implementation and Evaluation of an Arithmetic Pipeline on FLOPS-2D: Multi-FPGA system ]
\n\u6700\u521d\u306e\u3072\u3068\u304c\u3044\u306a\u304f\u3066\u3044\u304d\u306a\u308a\u308f\u3057\u3089\u3002
\n\u7cbe\u5ea6\u3092\u5909\u3048\u308b\u3053\u3068\u306f\u8003\u3048\u305f? \u2192 double precision \u304c minimum requirement \u306a\u306e\u3067\u3002
\nIFC \u3068 g95 \u30674\u500d\u901f\u5ea6\u304c\u9055\u3046\u306e\u306f\u306a\u305c\uff1f \u2192 SSE\u3068\u304b\u4f7f\u3063\u3066\u3044\u308b\u304b\u3082\u3002dualcore?
\n\u767a\u8868\u304a\u3064\u304b\u308c\u3055\u307e\u3067\u3057\u305f\u3002
\n[ Efficient Reconfigurable Design for Pricing Asian Options ]
\nStochastic simulation (single precision) on XC5VLX330T @ 200MHz, 34W.
\n– 313x Xeon quad-core, 80W
\n– 2.2x Tesla C1060, 200W
\n[ An FPGA-based fast classifier with high generalization property ]
\nCyclone vs Stratix vs Athlon. Power, cost, performance.
\nDSP unit \u306f\u4f7f\u3063\u305f? \u2192 \u4f7f\u3063\u3066\u306a\u3044\u3002LUT \u3067\u5168\u90e8\u3064\u304f\u308b\u306e\u304c natural \u3060\u3068\u601d\u3046\u3002
\nCombinational circuit \u3060\u3051\u3067\u3001pipeline \u306b\u306f\u306a\u3063\u3066\u3044\u306a\u3044\u3002
\nScaling \u3068\u304b\u306f? \u2192 future work \u3067\u3059\u3002
\n[[ Session 2: Frameworks ]]
\n[Dynamic Vectorization in the E2 Dynamic Multicore Architecture]
\nMicrosoft \u306f\u30d7\u30ed\u30bb\u30c3\u30b5\u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3\u3082\u3084\u3063\u3066\u3044\u308b\u306e\u304b\u30fb\u30fb\u30fb
\n32cores per chip.
\n\u5168\u90e8\u306e\u30b3\u30a2\u304c single precision FP \u3092\u6301\u3063\u3066\u3044\u308b\u3002power gating \u3068\u304b\u3002
\n[Binary acceleration using coarse-grained reconfigurable architecture]
\nHow many bits for configuration \u2192 basically instruction. 20bits.
\n[Implementation of a Programming Environment with a Multithread Model for Reconfigurable Systems]
\nSRC-6. \u3084\u3063\u3071\u50d5\u3082 streaming DMA \u3068\u304b\u5b9f\u88c5\u3057\u306a\u3044\u3068\u30c0\u30e1\u304b\u306d\u3002\u3080\u30fc
\n\u30ec\u30b8\u30b9\u30bf\u3078\u306e\u30a2\u30af\u30bb\u30b9\u306f\u3069\u3046\u3084\u3063\u3066\u691c\u51fa\u3059\u308b\u306e? \u2192 Carte\u3067\u306f\u57fa\u672c\u7684\u306b\u5909\u6570\u304c\u30ec\u30b8\u30b9\u30bf\u3067\u3001\u30aa\u30f3\u30dc\u30fc\u30c9\u30e1\u30e2\u30ea\u3078\u306e\u30a2\u30af\u30bb\u30b9\u306b\u306f\u7279\u5225\u306a\u8a18\u8ff0\u304c\u5fc5\u8981\u3002
\n[Runtime Multitasking Support on Reconfigurable Accelerators]
\nprofiler \u306e\u7d50\u679c\u306b\u57fa\u3065\u3044\u3066\u3054\u308a\u3054\u308a\u3002dso (dlopen()) \u3092\u4f7f\u3063\u3066\u5b9f\u88c5\u3057\u3066\u3044\u308b\u3002\u304b\u3063\u3053\u3044\u30fc
\n[Programming Framework for Clusters with Heterogeneous Accelerators]
\nLuk\u5148\u751f\u76f4\u3005\u306b\u3054\u767a\u8868\u3002
\n(Phenom X4 + Tesla + V5LX330T) x 16
\n[[ Session 3: Accelerators ]]
\n[An efficient CELL library for Lattice Quantum Chromodynamics]
\ndouble precision \u304c\u5fc5\u8981\u3060\u3068\u3044\u3063\u305f\u3051\u3069 double \u3067\u3084\u3063\u3066\u3044\u308b\u306e\uff1f \u2192 yes. penalty\u304c\u3042\u308b\u3088\u3002
\n[Software-based predication for AMD GPUs]
\nGPU \u3067\u306f control flow \u3068\u304b\u306e\u30da\u30ca\u30eb\u30c6\u30a3\u304c\u5927\u304d\u3044\u306e\u3067\u3001ALU packing \u3057\u305f\u308a\u5206\u5c90\u3068\u304b\u306e\u4e88\u6e2c(\u3068\u3044\u3046\u304b\u3001control flow clause \u306e\u7d71\u5408) \u3092\u3084\u3063\u3068\u3044\u3066\u6027\u80fd\u3092\u4e0a\u3052\u307e\u3057\u3087\u3046\u7684\u306a\u304a\u8a71\u300210% \u3068\u304b\u3001\u3059\u3054\u3044\u306e\u3060\u3068 50% \u304f\u3089\u3044\u306e\u52b9\u679c\u304c\u3042\u308b\u3002
\n[Multipliers for Floating-Point Double Precision and Beyond on FPGAs]
\n\u591a\u500d\u9577\u306a\u4e57\u7b97\u3067 DSP block \u306e\u4f7f\u7528\u91cf\u3092\u6291\u3048\u305f\u3044\u3002DSP48E \u306f 18x25bit \u306e\u975e\u5bfe\u79f0\u69cb\u6210\u3002\u3053\u308c\u3092\u4f7f\u3063\u3066\u3001\u90e8\u5206\u7a4d\u3092\u3046\u307e\u304f\u8a70\u3081\u8fbc\u3080: Automated tiling.
\nLogicore \u306e FP multiplier \u3088\u308a DSP block \u306e\u6570\u304c\u6e1b\u3063\u3066\u3001\u3057\u304b\u3082\u901f\u304b\u3063\u305f\u308a\u3059\u308b\u3002\u3053\u308c\u306f\u304b\u3063\u3053\u3044\u3044\u3002
\n[Prototype Implementation of Array-Processor Extensible over Multiple FPGAs for Scalable Stencil Computation]
\n\u4f50\u91ce\u5148\u751f\u306e\u3068\u3053\u308d\u306e\u3001GALS array \u306e\u8a71\u3002
\njitter \u3068\u304b\u304b\u3089\u5fc5\u8981\u306a FIFO \u306e\u6df1\u3055\u306f estimate \u3067\u304d\u308b? \u2192 6\u6bb5\u304f\u3089\u3044\u3002
\n[[ Invited talk 2: Custom Computing for Efficient Acceleration of HPC Kernels ]]
\nBandwidth \u3068 arithmetic performance \u306e\u30d0\u30e9\u30f3\u30b9\u304c\u5927\u4e8b\uff01
\n– Custom computing \u3067\u89e3\u6c7a\u3057\u307e\u3057\u3087\u3046
\n– Roofline: an insightful visual performance model for multicore architectures<\/a> \u304c\u7d39\u4ecb\u3055\u308c\u3066\u305f\u3002\u9762\u767d\u305d\u3046\u3002\u3042\u3068\u3067\u8aad\u3082\u3046\u3002
\n– Real time data compression to get more bandwidth.
\n– cubic predictor \u3092\u4f7f\u3063\u3066\u3001CFD \u3067 4x bandwidth \u3068\u304b\u51fa\u3057\u3066\u3044\u308b\u3002\u3053\u308c\u306f\u30c7\u30fc\u30bf\u306e\u4e2d\u8eab\u306b\u3088\u308b\u304b\u3089\u306a\u3093\u3068\u3082\u3044\u3048\u306a\u3044\u3051\u3069\u3001\u9811\u5f35\u3063\u3066\u3084\u3063\u3066\u307f\u308b\u4fa1\u5024\u306f\u3042\u308b\u306a\u3002
\n31bit \u306e custom FP format \u3092\u4f7f\u3063\u3066\u3044\u308b\u306e\u306f\u3069\u3046\u3057\u3066? \u2192 fraction \u30921\u30d3\u30c3\u30c8\u524a\u3063\u305fIEEE754.<\/p>\n","protected":false},"excerpt":{"rendered":"

accept ratio was 54%. [[ Session 1: FPGA-based Applications ]] [ Implementation and Evaluation of an Arithmeti … “HEART 2010” \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":""},"categories":[10],"tags":[],"class_list":["post-2580","post","type-post","status-publish","format-standard","hentry","category-conference-logs"],"_links":{"self":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2580","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/comments?post=2580"}],"version-history":[{"count":0,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2580\/revisions"}],"wp:attachment":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/media?parent=2580"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/categories?post=2580"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/tags?post=2580"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}