{"id":2485,"date":"2009-12-12T03:00:45","date_gmt":"2009-12-11T18:00:45","guid":{"rendered":"http:\/\/yasu2.prosou.nu\/blog\/index.php\/2009\/12\/12\/reconfig_09\/"},"modified":"2009-12-12T03:00:45","modified_gmt":"2009-12-11T18:00:45","slug":"reconfig_09","status":"publish","type":"post","link":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2009\/12\/12\/2485\/","title":{"rendered":"ReConFig &#8217;09"},"content":{"rendered":"<p>[Opening]<br \/>\n&#8211; 131 submitted papers<br \/>\n&#8211; 42 full papers<br \/>\n&#8211; 35 posters<br \/>\n&#8211; 4 from Japan (5\u4f4d\u304f\u3089\u3044)<br \/>\n[ Keynote 1 ]<br \/>\nSemiconductor in transition:<br \/>\n&#8211; 32nm scheduled to debut by 2010<br \/>\n&#8211; 22nm is deemed feasible<br \/>\n&#8211; fewer, new architectures on the latest processes<br \/>\n&#8211; programmability and concurrency are the new imperatives<br \/>\nParallel processing becomes Chip-level Multi-core processing (CMP)<br \/>\n&#8211; Power dissipation is a dominant, cross-cutting concern<br \/>\nXilinx vision: fabless &#038; programmability.<br \/>\n\u3088\u304f\u8003\u3048\u308b\u3068\u3042\u3042\u3044\u3046\u6700\u5148\u7aef\u306e\u30c1\u30c3\u30d7\u3092 fabless vendor \u304c\u4f5c\u308b\u3063\u3066\u3059\u3054\u3044\u3002<br \/>\nSPARTAN-6 \u3067\u306f\u6614\u306e\u3088\u3046\u306b\u3001Parallel I\/O \u306f\u5916\u5468\u306b\u914d\u7f6e\u3055\u308c\u3066\u3044\u308b\u304c\u3001Virtex-6 \u3067\u306f\u5185\u5074\u306b\u3042\u308b\u3002\u304b\u3063\u3053\u3044\u3044\u3002<br \/>\n\u6d88\u8cbb\u96fb\u529b\u306f\u6700\u5927\u3067 65% \u6e1b\u3063\u3066\u3044\u308b\u3002<br \/>\nLinux 2.6.30 included the MicroBlaze architecture for the first time in a mainstream kernel release! \u307e\u3058\u304b!!<br \/>\nQEMU + PetaLinux \u3067\u3001\u5b9f\u6a5f\u304c\u306a\u304f\u3066\u3082\u30c7\u30d0\u30c3\u30b0\u3067\u304d\u308b\u3002<br \/>\n<iframe loading=\"lazy\" title=\"PetaLinux SDK v1.1 QEMU and Virtual Networking Demo\" width=\"840\" height=\"630\" src=\"https:\/\/www.youtube.com\/embed\/f3cC44OPZ1M?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture\" allowfullscreen><\/iframe><br \/>\nEmbedded Software design cost already exceeds hardware design cost.<br \/>\n\u4e26\u5217\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u304c\u554f\u984c\u3002<br \/>\nConcurrent software compiler: enables compilation and SW development in highly parallel processing SOCs. Productivity +200% in SW. Expected in 2013.<br \/>\n[ General Session 1: Arithmetics ]<br \/>\n&#8211; FPGA implementation of decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier<br \/>\n10\u9032\u3067\u3059\u3002<br \/>\niEEE754-2008 \u306e decimal64 data format. BCD\u4f7f\u3063\u3066\u8a08\u7b97\u3059\u308b\u3002<br \/>\nVirtex-II Pro \u3067\u306e\u5468\u6ce2\u6570\u306f 70MHz+ \u3067\u3001\u60aa\u304f\u306a\u3044\u3002\u30d1\u30a4\u30d7\u30e9\u30a4\u30f3\u6bb5\u6570\u306f 11.<br \/>\n&#8220;It makes me nervous to fly on airplanes, since I know they are designed using floating-point arithmetic&#8221; Alston Scott Householder.<br \/>\n&#8211; Runtime memory allocation in a heterogeneous reconfigurable platform<br \/>\nTUDelft \u306e\u4eba\u3002<br \/>\n\u3057\u304b\u3057\u308f\u3057\u3001\u3053\u3046\u3044\u3046\u8a71\u306f\u308f\u304b\u3089\u3093\u3061\u3085\u3046\u306b\u3002<br \/>\n&#8211; Hotspot Mitigation using Dynamic Partial Reconfiguration for Improved Performance<br \/>\nTemperature distribution is not uniform \u2192 Temperature controlled reconfiguration \u3092\u3057\u307e\u3057\u3087\u3046\u3001\u3068\u3044\u3046\u8a71\u3002\u6e29\u5ea6\u306f ring oscillator \u3067\u6e2c\u308b\u306e\u304b!<br \/>\n\u305d\u308c\u3067\u3001\u3057\u3093\u3069\u3044\u3068\u3053\u308d\u3092\u79fb\u52d5\u3055\u305b\u308b\u3053\u3068\u3067\u3001\u5168\u4f53\u306e\u767a\u71b1\u3092\u6291\u3048\u308b\u3053\u3068\u304c\u3067\u304d\u308b\u3089\u3057\u3044\u3002\u7d50\u679c\u3068\u3057\u3066\u901f\u3044\u5468\u6ce2\u6570\u306e\u307e\u307e\u52d5\u304b\u305b\u3066\u30b9\u30eb\u30fc\u30d7\u30c3\u30c8\u304c\u4e0a\u304c\u308b\u306e\u304b\u3002\u306a\u308b\u307b\u3069\u30fc\u3002<br \/>\n&#8211; A systolic array based architecture for implementing multivariate polynomial interpolation tasks<br \/>\n\u306a\u3093\u304b\u30d7\u30ed\u30b0\u30e9\u30e0\u3068\u9055\u3046\u305e\u3001\u3068\u8003\u3048\u3066\u3044\u3066\u3001Session 1 \u3068 2 \u304cfuse \u3055\u308c\u3066\u3044\u308b\u3001\u3068\u3044\u3046\u3053\u3068\u306b\u3084\u3063\u3068\u304d\u3065\u3044\u305f\u3002<br \/>\n\u3069\u3046\u3044\u3046\u3053\u3068\u3060\u30fb\u30fb\u30fb<br \/>\n[ General Session 3: New FPGA Architectures ]<br \/>\n&#8211; A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA.<br \/>\nXilinx \u306e QPro \u30b7\u30ea\u30fc\u30ba\u3067\u306f 4SEU\/Day \u304f\u3089\u3044\u3002<br \/>\nTMR + Scrubbing \u304c\u5fc5\u8981\u304b\u306a\u3002<br \/>\nSEU-hardened CSRAM \u3068\u3044\u3046\u306e\u3092\u63d0\u6848\u3002<br \/>\nPMOS \u30c8\u30e9\u30f3\u30b8\u30b9\u30bf\u3092\u5165\u308c\u3066\u30018\u30c8\u30e9\u30f3\u30b8\u30b9\u30bf\/Cell \u306b\u306a\u308b\u3051\u3069\u3001\u3053\u308c\u306a\u3089\u305d\u308c\u307b\u3069\u5927\u304d\u304f\u306a\u3044\u3088\u306d\u3001\u3068\u3044\u3046\u8a71\u3002<br \/>\n6-T SRAM \u3060\u3068 29um^2 \u304f\u3089\u3044\u3060\u3051\u3069\u3001\u3053\u306e\u3084\u308a\u304b\u305f\u3060\u3068 32um^2 \u304f\u3089\u3044\u3001\u3060\u3068\u601d\u3063\u305f\u3002\u6570\u5b57\u9593\u9055\u3063\u3066\u305f\u3089\u3054\u3081\u3093\u306a\u3055\u3044\u3002\u3067\u3082\u3001\u30aa\u30fc\u30d0\u30fc\u30d8\u30c3\u30c9\u306f 10% \u304f\u3089\u3044\u3002<br \/>\nSEU \u304c\u8d77\u304d\u308b threshold \u307f\u305f\u3044\u306a\u306e\u306f MeV \u3067\u6e2c\u308b\u306e\u304b\u3057\u3089\u3093\uff1f<br \/>\n\u52c9\u5f37\u3057\u306a\u3044\u3068&#8230;<br \/>\n&#8211; MRAM based eFPGAs: Programming and silicon flows, &#8230;<br \/>\nSRAM is fast, easy to reconfigure, but volatile.<br \/>\nFlash is nonvolatile, but slow.<br \/>\nMRAM is&#8230; wow.<br \/>\nshadow reconfiguration: update magnetic information independently from the latch configuration (change committed later).<br \/>\nSR \u3068\u304b\u306f\u666e\u901a\u306b\u3067\u304d\u308b\u3063\u307d\u3044\u3002<br \/>\n[ Session HPC1: Track on High-Performance Reconfigurable Computing ]<br \/>\n&#8211; A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation<br \/>\nFPGA \u3092\u4f7f\u3046\u5834\u5408\u306b\u3057\u3093\u3069\u3044\u306e\u306f\u30dd\u30a4\u30f3\u30bf\u3092\u4f7f\u3063\u305f\u9593\u63a5\u30a2\u30af\u30bb\u30b9\u3067\u3001\u30a2\u30af\u30bb\u30b9\u30d1\u30bf\u30fc\u30f3\u304c irregular \u306b\u306a\u308b\u306e\u3067\u9045\u304f\u306a\u308b\u3002\u9593\u306b traversal cache \u3092\u5165\u308c\u3066\u3001\u3046\u307e\u304f\u30d0\u30f3\u30c9\u5e45\u3092\u7a3c\u3052\u308b\u3088\u3046\u306b\u3057\u305f\u3044\u3002<br \/>\n\u666e\u901a\u306e traversal cache \u306f\u540c\u3058\u30a2\u30af\u30bb\u30b9\u30d1\u30bf\u30fc\u30f3\u304c\u7e70\u308a\u8fd4\u3055\u308c\u308b\u5834\u5408\u306b\u52b9\u679c\u304c\u3042\u308b\u304c\u3001\u305d\u308c\u3067\u306f\u305f\u3044\u3066\u3044\u306f\u3046\u307e\u304f\u3044\u304b\u306a\u3044\u3002\u305d\u3053\u3067\u3001\u4f3c\u305f\u3088\u3046\u306a\u30a2\u30af\u30bb\u30b9\u30d1\u30bf\u30fc\u30f3\u3067\u3082\u52b9\u304f\u3088\u3046\u306b\u6539\u5584\u3002<br \/>\nn\u4f53\u554f\u984c\u3067\u306f\u3046\u307e\u304f\u30a2\u30af\u30bb\u30b9\u30ec\u30a4\u30c6\u30f3\u30b7\u3092\u96a0\u853d\u3067\u304d\u305f\u305d\u3046\u3060\u3002<br \/>\n\u6ff1\u7530\u3055\u3093\u306e\u5b9f\u88c5\u3082\u53c2\u8003\u306b\u3057\u305f\u3089\u3069\u3046\u3088\u3001\u3068\u5e73\u6728\u5148\u751f\u3002<br \/>\n&#8211; Triple line-based playout for Go<br \/>\n\u7881\u3063\u3066\u3088\u304f\u308f\u304b\u3063\u3066\u306a\u304b\u3063\u305f\u3093\u3067\u3059\u304c\u3001\u306a\u3093\u304b\u7406\u89e3\u3057\u305f\u6c17\u304c\u3059\u308b\u3002<br \/>\n\u3072\u3068\u3064\u77f3\u3092\u7f6e\u3044\u305f\u3068\u304d\u306b\u304c\u3089\u3063\u3068\u5834\u304c\u304b\u308f\u308b\u3053\u3068\u304c\u3042\u308b\u306e\u3067\u3001\u5b9f\u88c5\u306f\u3051\u3063\u3053\u3046\u96e3\u3057\u3044\u3002<br \/>\n\u7881\u76e4\u30923\u6bb5\u305a\u3064\u306b\u308f\u3051\u3066\u30b9\u30ad\u30e3\u30f3\u3059\u308b\u306e\u306f\u300119&#215;19\u3060\u3068\u3067\u304b\u3059\u304e\u308b\u304b\u3089\u3002<br \/>\n\u30bd\u30d5\u30c8\u30a6\u30a7\u30a2\u306e\u500d\u304f\u3089\u3044\u51fa\u3066\u3044\u308b\u304c\u3001\u3053\u3046\u3044\u3046\u554f\u984c\u3067\u306f\u6027\u80fd\u3067\u306a\u3055\u305d\u3046\u306a\u306e\u3067\u3001\u3059\u3054\u3044\u306e\u304b\u3082\u3002<br \/>\n&#8211; Scalability Studies of the BLASTn Scan and Ungapped Extention Functions<br \/>\nUniv. of North Carolina at Charlotte<br \/>\n\u304b\u306a\u308a\u901f\u3044\u3002\u30d9\u30f3\u30c1\u30de\u30fc\u30af\u306b\u306f\u3000env_nt \u3068\u304b env_nr database \u3092\u4f7f\u3063\u3066\u3044\u308b\u306e\u3067\u3001scalability issue \u306f\u554f\u984c\u306a\u3055\u305d\u3046\u3060\u3002\u51e6\u7406\u306f NCBI BLAST \u306b\u6e96\u3058\u3066\u3044\u308b\u3068\u306e\u3053\u3068\u3002\u30c7\u30fc\u30bf\u30bb\u30c3\u30c8\u3082\u73fe\u5b9f\u7684\u3060\u3057\u3001\u4fa1\u683c\u5bfe\u6027\u80fd\u6bd4\u306a\u3093\u304b\u3082\u793a\u3057\u3066\u304a\u308a\u3001\u975e\u5e38\u306b\u597d\u611f\u304c\u6301\u3066\u308b\u3002<br \/>\nTimeLogic Decypher Machine \u3068\u3044\u3046\u306e\u3092\u6bd4\u8f03\u306b\u4f7f\u3063\u3066\u3044\u308b\u3051\u3069\u3001\u3053\u308c\u306a\u3093\u3060\u308d\u3002Quad-core Xeon \u3068 FPGA \u304c\u8f09\u3063\u3066\u3044\u308b\u3089\u3057\u3044\u3002<a href=\"http:\/\/www.timelogic.com\/decypher_intro.html\">\u3053\u308c<\/a> \u304b\u3002<br \/>\n\u914d\u5217\u95a2\u4fc2\u306f\u30d0\u30f3\u30c9\u5e45\u304c\u624b\u5f37\u3044\u306e\u3067\u3084\u3089\u305a\u306b\u304d\u305f\u3093\u3060\u304c\u3001\u6700\u8fd1\u306f PCIe \u3068\u304b\u3042\u308b\u3057\u3001\u3084\u3063\u3066\u307f\u308b\u304b\u306a\u30fc\u3002<br \/>\n&#8211; Low power, reconfigurable computing platform for spacecraft<br \/>\nHigh throughput, radiation tolerant and low power. Streaming \u51e6\u7406\u3068\u304b\u3057\u305f\u3044\u3002<br \/>\nFPPA: Field programmable processor array<br \/>\nNASA \u3068\u7d44\u3093\u3067\u3044\u308b\u3002<br \/>\n[ Poster 1 ]<br \/>\n&#8211; Prevention of hot spot development on coarse-grained DR architectures<br \/>\n&#8211; Floating point hardware for embedded processors in FPGAs: Design space exploration for performance and area<br \/>\n&#8211; A 10Gbps OTN framer implementation targeting FPGA devices<br \/>\n&#8211; FPGA implementations of BCD multipliers<br \/>\n&#8211; Matrix multiplication based on scalable macro-pipelined FPGA accelerator<br \/>\n&#8211; PCIREX: a fast prototyping platform for TMR DR systems<br \/>\n&#8211; Speeding up fault injection for asynchronous logic by FPGA-based emulation<br \/>\n&#8211; Base-calling in DNA pyrosequencing with reconfigurable bayesian network<br \/>\n\u6700\u5f8c\u306e\u3084\u3064\u306b\u8208\u5473\u304c\u3042\u3063\u305f\u306e\u3067\u3059\u304c\u3001cancel \u3063\u307d\u3044\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[Opening] &#8211; 131 submitted papers &#8211; 42 full papers &#8211; 35 posters &#8211; 4 from Japan (5\u4f4d\u304f\u3089\u3044)  &hellip; <a href=\"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2009\/12\/12\/2485\/\" class=\"more-link\"><span class=\"screen-reader-text\">&#8220;ReConFig &#8217;09&#8221; \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":""},"categories":[10],"tags":[],"class_list":["post-2485","post","type-post","status-publish","format-standard","hentry","category-conference-logs"],"_links":{"self":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2485","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/comments?post=2485"}],"version-history":[{"count":0,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2485\/revisions"}],"wp:attachment":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/media?parent=2485"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/categories?post=2485"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/tags?post=2485"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}