{"id":2180,"date":"2008-09-11T05:41:16","date_gmt":"2008-09-10T20:41:16","guid":{"rendered":"http:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/11\/fpl_08_day_3\/"},"modified":"2008-09-11T05:41:16","modified_gmt":"2008-09-10T20:41:16","slug":"fpl_08_day_3","status":"publish","type":"post","link":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/11\/2180\/","title":{"rendered":"FPL &#8217;08: Day 3"},"content":{"rendered":"<p>[ Synthesis ]<br \/>\n#1: Floating Point Datapath Synthesis for FPGAs<br \/>\nAltera \u306e\u4eba\u306e\u30d7\u30ec\u30bc\u30f3\u30c6\u30fc\u30b7\u30e7\u30f3\u3002<br \/>\nFloating Point Compiler<br \/>\n\u30c7\u30fc\u30bf\u30d1\u30b9\u4e0a\u3067\u5fc5\u8981\u306a\u5024\u57df\u3084\u4f8b\u5916\u306f\u4e88\u6e2c\u3059\u308b\u3053\u3068\u304c\u3067\u304d\u308b\u306e\u3067\u3001\u3059\u3079\u3066\u306e\u30ce\u30fc\u30c9\u3092 IEEE754 \u306b\u5f93\u308f\u305b\u308b\u5fc5\u8981\u306f\u306a\u3044\u3002\u65b0\u3057\u3044\u6d6e\u52d5\u5c0f\u6570\u70b9\u578b\u3092\u5b9a\u7fa9\u3057\u3066\u3001\u305d\u308c\u3092\u4f7f\u3046\u3002\u6b63\u898f\u5316\u3068\u4f8b\u5916\u51e6\u7406\u306f\u3057\u306a\u3044 (\u4f8b\u5916\u691c\u51fa\u306f\u884c\u3044\u3001\u305d\u308c\u306f\u6b21\u306e\u30ce\u30fc\u30c9\u306b\u9001\u308b)\u3002\u6b63\u898f\u5316\u3068\u304b\u3057\u306a\u3044\u306e\u306f\u3001\u30d0\u30ec\u30eb\u30b7\u30d5\u30bf\u304c\u3084\u3070\u3044\u304b\u3089\u3002<br \/>\n&#8211; 200+ MHz double precision: 50GFLOPS &#8211; 3SE260<br \/>\n&#8211; 250+ MHz single precision: 100GFLOPS &#8211; 3SE260<br \/>\n\u3084\u3063\u3071\u6f14\u7b97\u5668\u306f\u4f5c\u3089\u306a\u304d\u3083\u3044\u3051\u306a\u3044\u3001\u3068\u3044\u3046\u3053\u3068\u3060\u306d\u3002\u3061\u3087\u3063\u3068\u53c2\u8003\u306b\u306a\u308a\u305d\u3046\u3060\u3002<br \/>\n#2: Automatic Generation of Run-time Parameterizable Configurations<br \/>\nTMAP: Tunable LUT mapping<br \/>\nFIR \u30d5\u30a3\u30eb\u30bf\u3068\u304b\u306e\u4fc2\u6570\u3092\u30ec\u30b8\u30b9\u30bf\u306b\u66f8\u3044\u3066\u6f14\u7b97\u5668\u3067\u51e6\u7406\u3059\u308b\u5f62\u5f0f\u304b\u3089\u3001\u6c7a\u3081\u3046\u3061\u306b\u3057\u305f\u56de\u8def\u306b reconfiguration \u3057\u3066\u4f7f\u3046\u65b9\u6cd5\u3002<br \/>\n&#8211; 1999LUTs \u2192 1008LUTs<br \/>\n&#8211; 8.4MHz \u2192 11.9MHz<br \/>\n\u3044\u3044\u3093\u3060\u3051\u3069\u3001configuration \u306b\u6642\u9593\u304c\u639b\u304b\u308b\u4e0a\u306b\u3001\u69cb\u6210\u60c5\u5831\u306e\u30c7\u30fc\u30bf\u30d9\u30fc\u30b9\u304c\u5927\u304d\u304f\u306a\u308b\u306e\u304c\u554f\u984c\u3002\u3053\u308c\u3092\u3001\u3046\u307e\u304f coefficient \u306b\u95a2\u4fc2\u3059\u308b\u3068\u3053\u308d\u3060\u3051\u30e9\u30f3\u30bf\u30a4\u30e0\u3067\u4f5c\u3063\u3066\u306a\u3093\u3068\u304b\u3059\u308b\u8a71\u3002<br \/>\n&#8211; 1301LUTs, 11.5MHz<br \/>\nVHDL \u306b annotation \u3092\u5165\u308c\u3066\u3001\u305d\u308c\u3092\u5408\u6210\u3059\u308b\u3088\u3046\u306a\u30c4\u30fc\u30eb\u3092\u958b\u767a\u3002<br \/>\n#3: Generation of partial FPGA configurations at run-time<br \/>\n\u52d5\u7684\u518d\u69cb\u6210\u3059\u308b\u30e2\u30b8\u30e5\u30fc\u30eb\u9593\u3092 Bus macro \u307f\u305f\u3044\u306a\u306e\u3067\u3001\u3064\u306a\u304e\u304b\u305f\u3092\u304d\u3081\u3066\u3057\u307e\u3046\u306e\u3067\u306f\u306a\u304f\u3066\u3001route table \u3092\u3082\u3064\u5171\u901a\u306e\u30a4\u30f3\u30bf\u30d5\u30a7\u30a4\u30b9\u3067\u63a5\u7d9a\u3059\u308b\u3053\u3068\u3067\u7c21\u5358\u306b\u3059\u308b\u3002<br \/>\nRoute table \u304c\u3082\u3064\u306e\u306f\u3001<br \/>\n&#8211; connection ID: relative coordinates of the endpoints<br \/>\n&#8211; route specification: list of frame and bit indices of all sw points in the route<br \/>\n&#8211; incompatibility information<br \/>\n\u305d\u3093\u306a\u611f\u3058\u3002<br \/>\n[ Optimization ]<br \/>\n#3: Memory access parallelization in high-level compilation for reconfigurable adaptive computers<br \/>\nAdaptive computing system: CPU + reconfigurable hardware<br \/>\n\u9ad8\u4f4d\u8a00\u8a9e\u304b\u3089\u306e\u5408\u6210\u306b\u95a2\u3059\u308b\u7814\u7a76\u306e\u591a\u304f\u306f\u79d1\u5b66\u6280\u8853\u8a08\u7b97 = regular memory access, loops with constant bounds, perfectly nested loops \u304c\u30bf\u30fc\u30b2\u30c3\u30c8\u3002\u305d\u3046\u3058\u3083\u306a\u3044\u3082\u306e\u3092\u6271\u3046\u306e\u306b\u554f\u984c\u306b\u306a\u308b\u306e\u306f\u3001\u30dd\u30a4\u30f3\u30bf\u3002<br \/>\ncontrol flow graph \u3092\u4f5c\u3063\u3066\u3001activate token \u3068 cancel token \u3092\u4f7f\u3046\u3002Token \u3092\u4f7f\u3046\u3053\u3068\u3067\u4f9d\u5b58\u95a2\u4fc2\u3092\u58ca\u3055\u305a\u306b\u30e1\u30e2\u30ea\u30a2\u30af\u30bb\u30b9\u3092\u4e26\u5217\u306b\u884c\u3063\u305f\u308a\u3001serialize \u3057\u305f\u308a\u3001speculation \u3057\u305f\u308a\u3059\u308b\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[ Synthesis ] #1: Floating Point Datapath Synthesis for FPGAs Altera \u306e\u4eba\u306e\u30d7\u30ec\u30bc\u30f3\u30c6\u30fc\u30b7\u30e7\u30f3\u3002 Floating Point Compiler \u30c7\u30fc\u30bf &hellip; <a href=\"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/11\/2180\/\" class=\"more-link\"><span class=\"screen-reader-text\">&#8220;FPL &#8217;08: Day 3&#8221; \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":""},"categories":[10],"tags":[35,42,41],"class_list":["post-2180","post","type-post","status-publish","format-standard","hentry","category-conference-logs","tag-fpga","tag-fpl-08","tag-reconfigurable-system"],"_links":{"self":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2180","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/comments?post=2180"}],"version-history":[{"count":0,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2180\/revisions"}],"wp:attachment":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/media?parent=2180"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/categories?post=2180"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/tags?post=2180"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}