Keynote 3 \u306f 8:30 \u304b\u3089… \u7121\u7406\u3067\u3059\u3002
\n[ Compilers for Reconfigurable Architectures ]
\n#2: CHiMPS: A C-Level Compilation Flow for Hybrid CPU\/FPGA Architectures
\nXeon \u306e\u30bd\u30b1\u30c3\u30c8\u306b\u633f\u3059 FPGA \u3092\u30bf\u30fc\u30b2\u30c3\u30c8\u306b\u8003\u3048\u3066\u3044\u308b\u3002
\nSpatial DFG \u306b\u3057\u3066\u4e26\u5217\u6027\u3092\u62bd\u51fa\u3057\u3066\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u5316\u3002
\n\u3069\u3053\u3092 HW \u306b\u843d\u3068\u3059\u304b\u306f pragma \u3092\u4f7f\u3063\u3066\u6307\u5b9a\u3059\u308b\u3002\u3042\u3068\u3001\u30dd\u30a4\u30f3\u30bf\u3092\u307b\u3052\u307b\u3052\u3059\u308b restrict \u3068\u3044\u3046\u30ad\u30fc\u30ef\u30fc\u30c9\u304c\u3042\u308b\u4ee5\u5916\u306f\u3001\u3075\u3064\u3046\u306e C \u8a00\u8a9e\u3002
\n\u30e1\u30e2\u30ea\u304b\u3089\u3068\u3063\u3066\u304f\u308b\u30c7\u30fc\u30bf\u3092\u30ad\u30e3\u30c3\u30b7\u30e5\u3059\u308b\u305f\u3081\u306e\u30e1\u30e2\u30ea\u3092\u305f\u304f\u3055\u3093\u7528\u610f\u3059\u308b\u3002\u3053\u308c\u3067\u30ec\u30a4\u30c6\u30f3\u30b7\u3092\u4e0b\u3052\u305f\u308a\u3001\u7af6\u5408\u3092\u6e1b\u3089\u3057\u305f\u308a\u3059\u308b\u3002\u30ad\u30e3\u30c3\u30b7\u30e5\u306e\u4e00\u8cab\u6027\u3092\u7dad\u6301\u3059\u308b\u30d7\u30ed\u30c8\u30b3\u30eb\u306f\u3061\u3083\u3093\u3068\u3084\u308b\u3068\u30b3\u30b9\u30c8\u304c\u5927\u304d\u3044\u306e\u3067\u3001\u66f8\u304d\u8fbc\u307f\u304c\u3067\u304d\u308b\u306e\u306f\u4e00\u5ea6\u306b\u3072\u3068\u3064\u3060\u3051\u3002Direct mapped cache.
\n\u3046\u30fc\u3093\u3002C \u304b\u3089 design entry \u3059\u308b\u9650\u308a\u306f\u7d50\u5c40\u3001\u30ad\u30e3\u30c3\u30b7\u30e5\u3068\u304b\u305d\u3046\u3044\u3046 Von Neumann \u306e\u546a\u7e1b\u304b\u3089\u306f\u9003\u3052\u3089\u308c\u306a\u3044\u306e\u304b\u306a\u30fc\u3002
\n\u5c0f\u3055\u3044\u30ad\u30e3\u30c3\u30b7\u30e5\u304c\u305f\u304f\u3055\u3093\u3042\u308b\u3068\u3001\u305d\u308c\u3092\u30e1\u30e2\u30ea\u30b3\u30f3\u30c8\u30ed\u30fc\u30e9\u306b\u3064\u306a\u3050\u3068\u3053\u308d\u304c\u5927\u5909\u3058\u3083\u306a\u3044? \u2192\u305d\u3046\u3067\u3082\u306a\u3044\u305c\u30fc
\n\u30de\u30eb\u30c1\u30b3\u30a2\u3068\u306e\u95a2\u4fc2\u306f\uff1f\u2192 \u305d\u308c\u3082\u3084\u308a\u305f\u3044\u306d\u3002\u3042\u3068\u3001\u6d6e\u52d5\u5c0f\u6570\u70b9\u95a2\u4fc2\u3068\u304b\u306d\u3002
\n#3: Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming
\nMemory subsystem \u3068 loop level parallelism \u306e co design.
\n\u3069\u306e loop nest level \u3067\u4f7f\u308f\u308c\u308b\u30c7\u30fc\u30bf\u5316\u3067\u3001off-chip \u306b\u3059\u308b\u304b on-chip \u306b\u3059\u308b\u304b\u3092\u304d\u3081\u308b\uff1f
\n\u3080\u30fc\u3002\u3053\u3046\u3044\u3046\u3053\u3068\u306f\u8003\u3048\u3066\u3044\u308b\u306e\u3060\u304c\u3001\u3053\u306e\u7814\u7a76\u306e\u3088\u3046\u306b\u5b9a\u5f0f\u5316\u3059\u308b\u3068\u3053\u308d\u304c\u96e3\u3057\u305d\u3046…
\n\u30e1\u30e2\u30ea\u306e\u4f7f\u3044\u65b9\u3067\u30af\u30ed\u30c3\u30af\u5468\u6ce2\u6570\u306f\u304b\u308f\u308b\uff1f \u2192 \u5909\u308f\u308b\u3051\u3069\u3001\u30b5\u30a4\u30af\u30eb\u6570\u306e\u307b\u3046\u304c\u5b9f\u884c\u6642\u9593\u306b\u5bfe\u3057\u3066\u652f\u914d\u7684\u3002
\n[ Random # Generation & PLL ]
\n#1: Sampling from the Exponential Distribution using Independent Bernoulli Variates
\n\u56fa\u5b9a\u5c0f\u6570\u70b9\u306e\u3001\u6307\u6570\u5206\u5e03\u306e\u4e71\u6570\u3092\u4f5c\u308b\u65b9\u6cd5\u3002exp() \u3092\u4f7f\u308f\u306a\u3044\u3067\u9ad8\u901f\u306b\u3084\u308b\u3002
\n\u3088\u3057\u307f\u3055\u3093\u304c cite \u3055\u308c\u3066\u305f\u3002
\n\u5c06\u6765\u7684\u306b\u306f fixed-floating conversion \u3092\u4f7f\u308f\u305a\u306b\u3001\u76f4\u63a5\u306b\u6d6e\u52d5\u5c0f\u6570\u70b9\u306e\u5024\u3092\u51fa\u305b\u308b\u3088\u3046\u306b\u3057\u305f\u3044\u3002
\n#2: Enhancing security of ring oscillator-based TRNG implemented in FPGA
\nring osc \u3092\u4e71\u6570\u751f\u6210\u306b\u4f7f\u3046\u5834\u5408\u3001\u96fb\u6e90\u304b\u3089\u306e\u30ce\u30a4\u30ba\u3068\u304b\u304c\u3051\u3063\u3053\u3046\u554f\u984c\u3002\u6c17\u3092\u3064\u3051\u307e\u3057\u3087\u3046\u3002\u6c17\u3092\u3064\u3051\u3066\u5b9f\u88c5\u3059\u308c\u3070 deterministic jitter \u306f\u3051\u3063\u3053\u3046\u6e1b\u3089\u305b\u308b\u3002
\n[ Tutorial: Virtex-5 FXT: A new FPGA platform ]
\nVirte-5 FXT: has PPC440 instead of PPC405. Super-scaler, larger caches, deeper pipeline.
\nNot just a PPC440, but with: 5×2 crossbar connection, memory interface, 32bit DMA, user defined instruction (by APU), single\/double IEEE-754 compliant 128-bit FPU (soft core) …
\nGTX high-performance transceivers: 150Mbps to 6.5Gbps
\nPower dissipation = 250mW \/ channel or less
\nTXT Family: FX without PPC, but twice # of GTX transceivers. ES 4Q08, MP 1Q09.
\n8 to 24 transceivers for FXT family, 40 to 48 in TXT family.
\nDevice availability \u306e\u4fdd\u5b88\u306b\u3064\u3044\u3066\u306f\u3069\u3046\u8003\u3048\u3066\u3044\u308b?
\nXC3000 \u306f 15 \u5e74\u524d\u306e\u88fd\u54c1\u3067\u3001\u307e\u3060\u58f2\u3063\u3066\u308b\u3051\u3069\u3001\u3044\u307e\u304b\u3089\u30c7\u30b6\u30a4\u30f3\u3059\u308b\u306a\u3089\u3070\u65b0\u3057\u3044\u306e\u3092\u4f7f\u3044\u307e\u3057\u3087\u3046\u30021\u5e74\u306e FPGA \u306e\u9032\u6b69\u306f\u4eba\u9593\u306e15\u6b73\u5206\u3060\u3088!
\n\u3067\u3082\u3001binary compatible \u306b\u3059\u308b\u3053\u3068\u306f\u8003\u3048\u3066\u3044\u307e\u305b\u3093\u3002
\n[ High performance Computing for Financial and Biological Modeling ]
\n#1: FPGA Acceleration of Monte-Carlo Based Credit Derivative Pricing
\nsingle\/double precision floating point \u306e hybrid design \u3068\u304b\u3092\u3057\u3066\u3044\u308b\u3068\u3053\u308d\u304c\u9762\u767d\u305d\u3046\u3002\u69cb\u6210\u306e\u304a\u3082\u3057\u308d\u3055\u3067\u306f 443 \u3055\u3093\u306e\u4ed5\u4e8b\u306e\u307b\u3046\u304c\u305a\u3063\u3068\u4e0a\u3060\u306a\u3002
\n#3: Acceleration of a Production Rigid Molecure Docking Code<\/p>\n","protected":false},"excerpt":{"rendered":"