{"id":2149,"date":"2008-09-09T04:56:02","date_gmt":"2008-09-08T19:56:02","guid":{"rendered":"http:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/09\/fpl_08_day_1\/"},"modified":"2008-09-09T04:56:02","modified_gmt":"2008-09-08T19:56:02","slug":"fpl_08_day_1","status":"publish","type":"post","link":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/09\/2149\/","title":{"rendered":"FPL &#8217;08: Day 1"},"content":{"rendered":"<p>[ Opening Keynote ]<br \/>\nFPGA is the programmable platform for Transforming, transporting and computing digital data.<br \/>\nTriple play opportunity:<br \/>\n&#8211; DSP<br \/>\n&#8211; Packet processing<br \/>\n&#8211; Tera computing<br \/>\nNetwork Trends:<br \/>\n&#8211; Global IP traffic will reach 44bn gigabytes \/ month in 2012, while less than 7bn in 2007.<br \/>\n&#8211; Video goes 22% of consumer traffic in 2007, will be 90% in 2012.<br \/>\n&#8211; Mobile data traffic will roughly double each year from 2008-2012.<br \/>\n\u2192 focus on reducing power consumption to reduce operating expense.<br \/>\nStanford Open Slate Program<br \/>\n&#8211; Programmable Open Mobile Internet<br \/>\n&#8211; 25 Stanford inter-disciplinay faculty + Cisco, Deutsche Telekom, DoCoMo, NEC, Xilinx<br \/>\nVirtual operating system is available: next step is virtual network!<br \/>\n&#8211; High speed \/ reliability \/ security : various demands<br \/>\n&#8211; packet level reconfiguration !?<br \/>\n\u305d\u306e\u307b\u304b\u3044\u308d\u3044\u308d<br \/>\n&#8211; Packet based on-board interconnection<br \/>\n&#8211; MIMO, Multi mode radio \u3068\u304b\u306f\u4fe1\u53f7\u51e6\u7406\u306e\u91cf\u304c\u30e4\u30d0\u3044<br \/>\n&#8211; Heterogeneous multiprocessing: Intel + FPGA (on FSB)<br \/>\nUniversity Program:<br \/>\n&#8211; XUPV5-LX110T<br \/>\n&#8211; \u5468\u8fba\u56de\u8def\u3082\u308a\u3060\u304f\u3055\u3093\u3002PCIe \u3082\u3064\u3044\u3066\u308b\u3002\u3084\u3079\u3048\u3001\u697d\u3057\u305d\u3046<br \/>\n&#8211; OpenSPARC evaluation kit \u3082&#8230;<br \/>\n[ NoC session ]<br \/>\n#2<br \/>\nCoarse grain reconfigurable architecture + multistage interconnection<br \/>\nGood old MIN!<br \/>\n2-input 2-output \u3060\u3051\u3069\u3001\u5927\u304d\u3044\u306e\u306f\u8003\u3048\u306a\u304b\u3063\u305f?\u3000\u2192 \u305d\u306e\u3046\u3061\u306d\u30fc<br \/>\n#3<br \/>\nmany core \u306a\u30b7\u30b9\u30c6\u30e0\u3078\u5411\u3051\u305f\u304a\u8a71\u3002<br \/>\nprogrammable router \u3088\u308a NoC \u306e\u307b\u3046\u304c\u3044\u3044\u3088\u3001\u307f\u305f\u3044\u306a\u3002<br \/>\n\u306a\u3093\u304b\u3001\u4e21\u65b9\u3068\u3082\u308f\u308a\u3068\u666e\u901a\u306e\u8a71\u3060\u3063\u305f\u306e\u3067\u3001\u3061\u3087\u3063\u3068\u6b8b\u5ff5\u3002<br \/>\n[ Keynote #2, FPGAs at CERN ]<br \/>\nCERN \u3067\u306f\u52a0\u901f\u5668\u306e\u307e\u308f\u308a\u306e\u3001\u5927\u91cf\u306e\u691c\u51fa\u5668\u304b\u3089\u306e\u4fe1\u53f7\u3092\u51e6\u7406\u3059\u308b\u306e\u306b FPGA \u3092\u4f7f\u3063\u3066\u3044\u308b\u3002\u52a0\u901f\u5668\u306a\u306e\u3067\u3001\u5f53\u7136\u30e4\u30d0\u3044\u7c92\u5b50\u304c\u3044\u3063\u3071\u3044\u98db\u3073\u51fa\u3059\u308f\u3051\u3067\u3001radiation \u304c\u3059\u3054\u3044\u3068\u3053\u308d\u306f\u53e4\u3044\u30c1\u30c3\u30d7 (Virtex-II Pro \u3068\u304b) \u3092\u4f7f\u3063\u3066\u30a8\u30e9\u30fc\u7387\u3092\u4e0b\u3052\u308b\u307f\u305f\u3044\u306a\u8a71\u3057\u3082\u3002<br \/>\n[ Image &#038; Video ]<br \/>\nHow fast is an FPGA in image processing?<br \/>\n\u3053\u306e\u9593\u306e RECONF \u3067\u8074\u3044\u305f\u304a\u8a71\u3068\u3060\u3044\u305f\u3044\u540c\u3058\u3002\u30bd\u30d5\u30c8\u30a6\u30a7\u30a2\u306f Intel C++ \u4f7f\u3063\u3066\u8a55\u4fa1\u3057\u3066\u308b\u306e\u304b\u30fc\u3002\u3044\u3044\u304b\u3082\u3002<br \/>\nSIMD \u306f\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u304c\u5927\u5909\u3060\u3068\u3044\u3063\u3066\u3044\u305f\u304c\u3001\u4f7f\u308f\u306a\u304b\u3063\u305f\u3089 speedup \u306f\u3069\u3046\u306a\u308b\u304b\uff1f \u2192 \u6e2c\u5b9a\u3057\u3066\u306a\u3044\u3002\u30d7\u30ed\u30b0\u30e9\u30df\u30f3\u30b0\u306e\u5f97\u610f\u306a\u5b66\u751f\u304c\u5b9f\u88c5\u3057\u307e\u3057\u305f\u3002<br \/>\nDSP \u3068\u304b GPU \u3092\u4f7f\u308f\u306a\u3044\u306e\u306f\u306a\u305c? \u2192  intel \u306e\u30d7\u30ed\u30bb\u30c3\u30b5\u306f\u307f\u3093\u306a\u304c\u6301\u3063\u3066\u3044\u308b\u304b\u3089\u3002<br \/>\nFPGA Hardware Acceleration for H.264 Motion Estimation<br \/>\n\u30d5\u30ec\u30fc\u30e0\u309216&#215;16 \u306e\u30d6\u30ed\u30c3\u30af\u306b\u533a\u5207\u3063\u3066\u3001SAD \u304c\u6700\u5c0f\u306b\u306a\u308b\u3068\u3053\u308d\u3092\u898b\u3064\u3051\u3001motion vector \u3092\u6c42\u3081\u308b\u3002<br \/>\n256 subtraction+accumulation \/ SAD \u2192 96giga \/ sec.<br \/>\nH.264 \u3067\u306f\u30d6\u30ed\u30c3\u30af\u306e\u30b5\u30a4\u30ba\u3092\u30d5\u30ec\u30fc\u30e0\u5185\u306e\u5834\u6240\u3054\u3068\u306b\u9078\u3079\u308b\u3053\u3068\u3068\u3001\u8907\u6570\u306e\u30d5\u30ec\u30fc\u30e0\u3092 reference \u3068\u3057\u3066\u9078\u3079\u308b (\u9ce5\u304c\u7fbd\u3070\u305f\u3044\u305f\u308a\u3068\u304b\u3001\u305d\u3046\u3044\u3046 periodic motion \u3092\u3046\u307e\u304f\u6271\u3048\u308b\u3088\u3046\u306b\u306a\u308b\u3002\u305f\u3044\u3066\u3044\u306e\u5b9f\u88c5\u3067\u306f 4 \u3064\u306e reference frame \u3092\u4f7f\u3046) \u3053\u3068\u304c\u9055\u3046\u3002\u8a08\u7b97\u91cf\u306f 4 \u500d\u3061\u3087\u3063\u3068\u3002<br \/>\n1.5 giga macro-reference block access \/ sec\u3002\u30e1\u30e2\u30ea\u30a2\u30af\u30bb\u30b9\u3082\u6700\u9069\u5316\u3057\u306a\u3044\u3068\u3084\u3070\u3044\u3002<br \/>\nReal Time Image Super Resolution on an FPGA<br \/>\nImperial College \u306e\u3072\u3068\u3002\u3046\u304a\u30fc\u8d85\u89e3\u50cf\u3060!<br \/>\n\u8907\u6570\u306e\u4f4e\u89e3\u50cf\u5ea6\u306e\u30d5\u30ec\u30fc\u30e0\u304b\u3089\u9ad8\u89e3\u50cf\u5ea6\u306e\u30d5\u30ec\u30fc\u30e0\u3092\u5408\u6210\u3059\u308b\u3002<br \/>\nFrequency domain approach \u3068 spacial domain approach \u304c\u3042\u308b\u3002\u3084\u3063\u305f\u306e\u306f\u5f8c\u8005 (\u3060\u3068\u601d\u3046)\u3002<br \/>\n1. Motion Estimation<br \/>\n2. Image Reconstruction<br \/>\n3. Image Quality: Deblurring, Denoising<br \/>\n\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u51e6\u7406\u306b\u9069\u3057\u305f SR \u30a2\u30eb\u30b4\u30ea\u30ba\u30e0\u3092\u958b\u767a\u3057\u305f\u30022, 3 \u3092\u5b9f\u88c5\u3057\u3066\u3044\u308b\u3002<br \/>\nXC2V6000 \u3067 1280&#215;720, 61fps \u51fa\u308b\u3002\u3044\u307e\u306e\u3068\u3053\u308d\u3001\u3075\u3064\u3046\u306e HDTV \u306b\u306f\u3053\u308c\u3067\u5145\u5206\u3060\u3057\u3001FPGA \u306e\u30ea\u30bd\u30fc\u30b9\u3092\u5168\u90e8\u4f7f\u3044\u5207\u3063\u3066\u3044\u308b\u308f\u3051\u3067\u306f\u5168\u7136\u306a\u3044\u306e\u3067\u3001\u3082\u3063\u3068\u5c0f\u3055\u3044\u306e\u3067\u3082\u8f09\u308a\u305d\u3046\u3002\u4e00\u756a\u5fc5\u8981\u306a\u8cc7\u6e90\u306f multiplier. \u56fa\u5b9a\u5c0f\u6570\u70b9\u3060\u304c\u3001\u6d6e\u52d5\u5c0f\u6570\u70b9\u306b\u3088\u308b\u5b9f\u88c5\u3068\u6bd4\u3079\u3066\u76ee\u306b\u898b\u3048\u308b\u9055\u3044\u306f\u306a\u3044\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"<p>[ Opening Keynote ] FPGA is the programmable platform for Transforming, transporting and computing digital dat &hellip; <a href=\"https:\/\/yasu2.prosou.nu\/blog\/index.php\/2008\/09\/09\/2149\/\" class=\"more-link\"><span class=\"screen-reader-text\">&#8220;FPL &#8217;08: Day 1&#8221; \u306e<\/span>\u7d9a\u304d\u3092\u8aad\u3080<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":""},"categories":[10],"tags":[35,42,41],"class_list":["post-2149","post","type-post","status-publish","format-standard","hentry","category-conference-logs","tag-fpga","tag-fpl-08","tag-reconfigurable-system"],"_links":{"self":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2149","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/comments?post=2149"}],"version-history":[{"count":0,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/posts\/2149\/revisions"}],"wp:attachment":[{"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/media?parent=2149"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/categories?post=2149"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/yasu2.prosou.nu\/blog\/index.php\/wp-json\/wp\/v2\/tags?post=2149"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}