Decoding Read Completion Boundary register of PCIe

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It's important to know the RCB, read completion boundary to decode the completion TLPs for read request.
The RCB configuration is written in the Link Control Register, bit 3. The bit is 1'b0 if the RCB of root complex is 64 bytes, and 1'b1 for 128 bytes.

FYI, the bit appears on cfg_lcommand[3] on Xilinx's Endpoint Block Plus.

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This page contains a single entry by Yasunori Osana published on February 25, 2010 7:20 PM.

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